1. Field of the Invention
This invention relates to a system and method for allowing high-speed testability of integrated devices.
2. Description of Background
When testing integrated circuits, techniques such as ABIST (Array Built In Self Test) and LBIST (Logic Build In Self Test) are used to test memory arrays and logic respectively. It is important to be able to test the full latch-to-latch paths that are used in the chip function. Many times the latch-to-latch paths cross macro boundaries that include static random access memories (SRAMs) along with other logic.
Domino SRAMs have a feature where the access time is determined by the slowest SRAM cell unlike a sense amplifier SRAM where the access time is determined by fixed timing on the sense amp set signal. Because of this, a problem exists when testing domino SRAMs that have logic between the output of the array and a scannable capture latch. In these situations, ABIST can often only test the read path to the array boundary and a simple bypass path is used to the test the downstream logic during LBIST. Since neither ABIST nor LBIST tests the entire array and logic path simultaneously there is a test hole where AC or high-speed faults or slow SRAM cells can remain undetectable and the part (SRAM) will fail in normal functional operation. When these cases occur, architectural verification programs (AVPs) are often required to close the hold at the expense of test time and cost.